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<a href="#pub-attribs">成员变量</a>  </div>
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<div class="title">TIM_TypeDef结构体 参考<div class="ingroups"><a class="el" href="group___c_m_s_i_s.html">CMSIS</a> &raquo; <a class="el" href="group__wb32l003.html">Wb32l003</a> &raquo; <a class="el" href="group___device___peripheral__peripherals.html">Device_Peripheral_peripherals</a></div></div>  </div>
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成员变量</h2></td></tr>
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<h2 class="groupheader">结构体成员变量说明</h2>
<a id="a3d62ac5e40ff5823b128a04ef782623d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3d62ac5e40ff5823b128a04ef782623d">&#9670;&nbsp;</a></span>ARR</h2>

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<p>TIM auto load register, Address offset: 0x02C </p>

</div>
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<h2 class="memtitle"><span class="permalink"><a href="#a56d7d3b93993c2d388a73f3307bbbced">&#9670;&nbsp;</a></span>BDTR</h2>

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<p>TIM brush and dead register, Address offset: 0x044 </p>

</div>
</div>
<a id="a24525d84ecd9667ecc8c37c5c463f95c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a24525d84ecd9667ecc8c37c5c463f95c">&#9670;&nbsp;</a></span>CCER</h2>

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<p>TIM captuer/compare enable register, Address offset: 0x020 </p>

</div>
</div>
<a id="a635ed2940c2707909365fd5d3f30ad25"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a635ed2940c2707909365fd5d3f30ad25">&#9670;&nbsp;</a></span>CCMR1</h2>

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<p>TIM capture/compare mode register 1, Address offset: 0x018 </p>

</div>
</div>
<a id="a3195c96fb54f7673e6ab03c4c9c89f80"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3195c96fb54f7673e6ab03c4c9c89f80">&#9670;&nbsp;</a></span>CCMR2</h2>

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<p>TIM capture/compare mode register 2, Address offset: 0x01C </p>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#aecb7c415dd48824653a1b0833fe720ce">&#9670;&nbsp;</a></span>CCR1</h2>

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<p>TIM captuer/compare register 1, Address offset: 0x034 </p>

</div>
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<a id="af67f9bd444779f12e7caa27c5310c874"></a>
<h2 class="memtitle"><span class="permalink"><a href="#af67f9bd444779f12e7caa27c5310c874">&#9670;&nbsp;</a></span>CCR2</h2>

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<p>TIM capture/compare register 2, Address offset: 0x038 </p>

</div>
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<a id="ae1c2362031fb85233c2307a9a2985c2b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae1c2362031fb85233c2307a9a2985c2b">&#9670;&nbsp;</a></span>CCR3</h2>

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<p>TIM capture/compare register 3, Address offset: 0x03C </p>

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</div>
<a id="aeca25330b0460bb45233c56fabfbfdc7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aeca25330b0460bb45233c56fabfbfdc7">&#9670;&nbsp;</a></span>CCR4</h2>

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          <td class="memname">__IOM uint32_t CCR4</td>
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<p>TIM capture/compare register 4, Address offset: 0x040 </p>

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<a id="ae8408c8a2f24dfd94de0083798b270fd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae8408c8a2f24dfd94de0083798b270fd">&#9670;&nbsp;</a></span>CNT</h2>

<div class="memitem">
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<p>TIM count register, Address offset: 0x024 </p>

</div>
</div>
<a id="a560b25d17498f4768655a99f0fa5dfc0"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a560b25d17498f4768655a99f0fa5dfc0">&#9670;&nbsp;</a></span>CR1</h2>

<div class="memitem">
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<p>TIM control register 1, Address offset: 0x000 </p>

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<a id="a08aa78fb433292d566a278fa65746dfd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a08aa78fb433292d566a278fa65746dfd">&#9670;&nbsp;</a></span>CR2</h2>

<div class="memitem">
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<p>TIM control register 2, Address offset: 0x004 </p>

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<a id="a51aecfb603179e8d6d9cc6e7516a902b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a51aecfb603179e8d6d9cc6e7516a902b">&#9670;&nbsp;</a></span>DIER</h2>

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<p>TIM interrupt enable register, Address offset: 0x00C </p>

</div>
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<a id="a0443543aeff9dc1b6aa2d243907279dc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0443543aeff9dc1b6aa2d243907279dc">&#9670;&nbsp;</a></span>EGR</h2>

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<p>TIM event trig register, Address offset: 0x014 </p>

</div>
</div>
<a id="a0b7228efee10f6e587d7e3b70a9f6ba7"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0b7228efee10f6e587d7e3b70a9f6ba7">&#9670;&nbsp;</a></span>PSC</h2>

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<p>TIM prescale register, Address offset: 0x028 </p>

</div>
</div>
<a id="a2d3e3514166bb9faca1c0c55ea602472"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2d3e3514166bb9faca1c0c55ea602472">&#9670;&nbsp;</a></span>RCR</h2>

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<p>TIM repeate count register, Address offset: 0x030 </p>

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<a id="a0b5df0c37a5031e2ca8bc45a68c97f10"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a0b5df0c37a5031e2ca8bc45a68c97f10">&#9670;&nbsp;</a></span>SMCR</h2>

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<p>TIM slave mode control register, Address offset: 0x008 </p>

</div>
</div>
<a id="a95fcc7996cf77f1fe70b6ad5bae01549"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a95fcc7996cf77f1fe70b6ad5bae01549">&#9670;&nbsp;</a></span>SR</h2>

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<p>TIM status register, Address offset: 0x010 </p>

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</div>
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